The present invention relates to a dynamic packet processor architecture that includes generic pipeline stages which may handle a variety of packet information.
Most conventional packet processors based systems, such as L2/L3/L4 switches and routers, include separate static and pre-defined input filters, route filters and output filters. Each filter is often only designed to perform one specific function and cannot handle a wide range of functions. Conventional router/switch systems are also designed to handle a predetermined number of processing steps.
Specialized processors and dedicated hardware are currently used to perform packet processing in today""s routers and switches. Each of these approaches represents some advantages and limitations. While specialized processors provide the flexibility to support new protocols and packet flows, they cannot handle line speed processing rates. The opposite is true for specialized hardware where flexibility is very limited but they can handle line speed processing rates.
If for example, the conventional packet processor based system has three fixed filters and is designed to handle three stages and the packet is non-conforming in that it requires more than three stages, then the conventional router systems cannot easily handle such a request and requires complicated re-looping mechanisms that dramatically slow down the processing of the non-conforming request. In many cases, the lookup tables of the input filters are relatively small which limits the global functionality and system flexibility. The approach of relying on a fixed number of filters that are each designed for a specific function unduly limits the flexibility and performance of the system when the required stages of incoming packets are not conforming to the specific design of the system. It is also often cumbersome to rely on many different specialized filters instead of generic filters that may handle almost any type of incoming packet type, packet flow and input port type.
The dynamic processor of the present invention provides a high degree of packet processing flexibility at line speed rates. More particularly, the dynamic packet processor architecture of the present invention includes a generic pipeline stage assembly in which every pipeline stage may be dynamically configured partly depending upon the packet type, the packet flow requirements and the input/output port type. In this way, the generic pipeline stages may be adjusted to the required processing stages and is designed for any packet flow, packet type and input/output port type. The input port types may, for example, include ethernet, POS (Packet Over Sonet), DTM (Dynamic Transfer Mode) and raw data. The raw data may be any input that is not using a predefined network protocol, i.e., voice data received by an E1/T1 framer. The configuration may be performed on a per packet flow basis so that, for example, the same stage may function as an input filter, route filter or as an output filter, as required.